Transition Capacitance and Diffusion Capacitance of Diode

Transition Capacitance CT of Diode (Space Charge Capacitance)

With the increase of the magnitude of reverse bias, majority carriers move away from the junction i.e. the width W of the depletion layer increases. This uncovered immobile charge on the two sides of the junction constitute a capacitor of incremental capacitance C_T is given by,

$C_T = |\dfrac{dQ}{dV}|$ ……..(1)

Where dQ is the increase in the charge resulting from an increase dV in voltage.

Hence, a voltage change dV in the time interval dt will result in a current i was given by,

$i = \dfrac{dQ}{dt} = C_T\dfrac{dV}{dt}$ ………(2)

This capacitance C_T is called the transition capacitance or space charge capacitance or barrier capacitance or depletion layer capacitance.

C_T forms an important parameter of the junction. However, C_T varies with the magnitude of the reverse bias. More the magnitude of the reverse bias greater is the width W of the depletion layer and smaller is the transition capacitance C_T.

C_T in a Step Graded Junction:

A junction is said to be step graded if there is an abrupt change from acceptor ion density on the P-side to donor ion density on the N-side. Such a junction gets formed in an alloyed junction (or Fused Junction) diode. In general, the acceptor density N_A and the donor density N_D are kept unequal. The transition capacitance C_T is then given by,

$C_T = \dfrac{\epsilon A}{W}$ ……..(3)

Where $\epsilon$ is an absolute permittivity of the semiconductor medium, A is the cross-sectional area of the junction and W is the of the depletion layer and is given by,

$W^2 = [\dfrac{2\epsilon V_j}{q}][\dfrac{1}{N_A}+\dfrac{1}{N_D}]$ ……..(4)

In case N_A>>N_D,

$W = (\dfrac{2\epsilon V_j}{N_Dq})^{\dfrac{1}{2}}$ ………..(5)

Hence, $C_T = A(\dfrac{N_D}{V_j})^{\dfrac{1}{2}} \times (\dfrac{q\epsilon}{2})^{\dfrac{1}{2}}$ ……….(6)

Thus, in a step graded junction, C_T is inversely proportional to the square root of junction voltage V_j where V_j is given by,

$V_j = V_o-V_d$ ……….(7)

Where V_d is a negative number indicating the applied reverse bias and V₀ is the contact potential.

C_T in a Linear Graded Junction

A junction is said to be linear graded if there is a linear variation of net charge density with distance in the transition region. Such a junction gets formed in a frown junction diode.

In such a junction diode also, the transition capacitance is given by,

$C_T = \dfrac{\epsilon A}{W}$ ………..(8)

Thus, the expression for C_Tfor the linearly graded junction is the same as for step graded junction.

However, in this case, assuming N_A = N_D, the width W of the depletion layer is given by,

$W = (\dfrac{6 \epsilon V_j}{q N_D})^{\dfrac{1}{2}}$ ………(9)

Hence,

$C_T = A(\dfrac{N_D}{V_j})^{\dfrac{1}{2}} \times (\dfrac{q\epsilon}{6})^{\dfrac{1}{2}}$ ……..(10)

Thus, in this case, also, C_T is inversely proportional to the square root of V_j.

Diffusion Capacitance or Storage Capacitance C_D

In the forward-biased diode, the potential barrier at the junction gets lowered. As a result, holes get injected from the P-side to the N-side and electrons get injected from the N-side to the P-side. These injected charges get stored near the junction just outside the depletion layer, holes in the N-region, and electrons in the P-region. Due to charge storage, the voltage lags behind the current producing the capacitance effect. Such a capacitance is called diffusion capacitance or storage capacitance C_D.

The diffusion capacitance C_D may be defined as the rate of change of injected charge with voltage,

Thus,

$C_D = \dfrac{dQ}{dV}$ ………..(11)

But, in a forward biased diode with one region say P-region very heavily doped relative to the other region (N region), current (I) is mainly due to holes. Then (I) is given by,

$I = \dfrac{Q}{\tau_p}$ …….(12)

Where Q is the stored charge and $\tau_p$ is the mean lifetime of hole and is given by,

$T_p = \dfrac{L_p^2}{D_p}$ ………….(13)

Where L_P is the diffusion length for holes, and D_P is the diffusion constant for holes.

Combining Equation (11) and (12), we get

$C_D = \tau \dfrac{dI}{dV} = \dfrac{\tau}{r}$ ……….(14)

But from equation of dynamic resistance $r \approx \dfrac{\eta V_T}{I}$ . Substituting this value of r in equation (14) we get,

$C_D = \dfrac{\tau I}{\eta V_T}$ ……….(15)

In a general case, diffusion constant C_D is caused by the diffusion of both the holes in the n-regions and electrons in the P-region, resulting in diffusion capacitance C_Dp and C_Dn respectively. The total diffusion capacitance C_D is the sum of C_Dp and C_Dn.

C_D may have a value of a few thousand pF. This time constant C_D. r mainly limits the frequency response of certain semiconductor devices when used in high-frequency applications.

In fact, in a forward diode, there are present both the diffusion capacitance C_D and the transition capacitance C_T, but C_D>>C_T. Typically, the C_D is more than a million times greater than C_T. Hence, in a forward-biased diode, C_T may be neglected and we need to consider only C_D.

Similarly, in reverse-biased diode, these are present both C_D and C_T. But C_D<<C_T. Hence, in a reverse-biased diode, we may neglect C_D and we need to consider only C_T.

For forward biased Ge diode $(\eta = 1)$ , at $I = 13 mA$ , $r = 2\Omega$ and then $C_D = 0.5\tau$ . For $\tau = 20 \mu s$ , $C_D = 10 \mu F$ .