Digital counters are frequently needed in all kinds of counting circuits, test gear, sequential displays, timers, etc for up to ten outputs (exclusive and independent), or 16 at the most. But the problem arises when it comes to using more than these many outputs.
In such a case, the 4017-based CMOS counter can be put to use as a 100-stage counter. The circuit configuration uses a dozen 4017 counter ICs.
IC12 sends clock pulses to IC11 at one tenth of its input frequency, which in turn allow Qa through Qj to go high in sequence. IC1 is activated first through Qa output, whose outputs Q0 to Q9 go high sequentially for the next ten pulses. It then turns the positive rail of IC1 to zero, and switches IC2 to active stage whose output go high for the next ten pulses. This continues until the 100th output goes high. In this way, the outputs Q0 through Q99 goes high one after the other, turning the pervious to low state in succession.
Thus a 100-stage counter may be implemented using a few discrete 4017s. If less than 100 outputs are needed, a counter stage may be dropped for every 10 outputs. The last needed output may be connected to the reset terminal (pin 15) of the 4017 counter.
IC1 – IC12 = CD4017