Pulse-width modulation (PWM), a form of PTM, is also known as pulse-duration modulation (PDM) and pulse-length modulation (PLM). A simple means of PWM generation is provided in figure 1 using 565 PLL. It actually creates PPM at a VCO output (pin 4), but by applying it and the input pulses to an Exclusive-OR gate, PWM is also created.
For the phase-locked loop (PLL) to remain locked, its VCO input (pin 7) must remain constant. The presence of an external modulating signal upsets the equilibrium. This causes the phase detector output to go up or down to maintain the VCO input (control) voltage. However, a change in phase detector output also means a change in phase difference between the input signal and the VCO signal. Thus, the VCO output has a phase shift proportional to the modulating signal amplitude. The PPM output is amplified by transistor T1 in figure 1 just prior to the output. The Exclusive-OR circuit provides a “high” output only when just one of its two inputs is “high”. Any other input condition produces a “low” output. By comparing the PPM signal and the original pulse input signal as inputs to the Exclusive-OR circuit, the output is a PWM signal at twice the frequency of the original input pulses.
Adjustment of VR1 varies the centre frequency of the VCO. The VR1 potentiometer may be adjusted to set up the quiescent PWM duty cycle. The output (PPM or PWM) of this circuit may then be used to modulate a carrier for subsequent transmission.
PARTS LIST OF PLL GENERATION OF PWM AND PPM
|Resistor (all ¼-watt, ± 5% Carbon)|
|R1 = 33 KΩR2, R3 = 390 Ω
R4 = 4.7 KΩ
R5 = 5.6 KΩ
R6 = 10 KΩ
R7 = 5 KΩ
VR1 = 6 KΩ
VR2 = 10 KΩ
|C1 = 0.1 µFC2 = 1000 pF
C3 = 0.001 µF
C4 = 0.01 µF
|IC1 = 565IC2 = 7486 (exclusive or gate)
T1 = 2N4123